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JTAGLive CoreCommander

JTAG CoreCom PR1b CoreCommander routines take control of key processor core (e.g. ARM, PPC, X-scale, Cortex etc.) functions using the built-in emulation/debug functions found in today’s RISC and DSP cores. They have been developed to speed-up board testing and debug by enabling kernel-centric testing. CoreCommander offer two modes of operation:

Interactive - offering direct control of the core or;
Python embedded - where controls can be scripted into a complete program.

JTAG Live Buzz is automatically included for free with this product.

  • JTAG control of µprocessors, and DSPs via core debug access
  • Most popular cores supported
  • Create cluster tests and flash applications

 

  • Overcomes deficiencies in boundary-scan registers
  • Works with devices not compliant to IEEE std 1149.x
  • Most popular processor cores supported (ARM PPC etc.)
  • Code compatible with Python for test scripting
  • Low-cost compared to other solutions.

 

  • Supported by JTAG Technologies, JTAG Live and FTDI based controllers/interfaces
  • Simple to use interactive GUI to perform core writes/reads
  • Functions include 'EnterDebug', 'ExitDebug', 'LoadMemory', 'SaveMemory', 'WritePC', 'ReadPC'
  • Compatible with Python open-source scripting language.
  • Works in tandem with JTAG Live Script - boundary-scan routines.
  • Please note that CoreCommander modules are priced per core.